Major tasks: - Development of IP cores for video coding / decoding and for CPU subsystems. - Implementig hardware modules from sofware source code on System Verilog, debugging. - Synthesis of hardware modules from C code using Vitis HLS, optimization of C code for achieving target performance and utilization. - Implementing the multi-threading feature in RISCV core. Remote job

Responsibility: - RTL design development and debuging (SoC, DSP and interface IP); - Synthesize RTL design in Cadence Genus, Innovus, using SDC files; - Development of verificarion environment for SoC and IP using SystemVerilog and UVM; - Development tests based on C, ASM and SysytemVerilog for SoC and IP RTL and netlists with SDF models; - Prototyping and debugging of the developed systems and modules using FPGA Xilinx (Virtex6, Spartan6, Kintex7); - Development of technical documentation; - Business trips; - Managing a team of 4 people; - Use the version control (svn, git) and project management (JIRA, Redmine). Achievements: - Participating in development of USB 2.0 HUB IC (top level assembly, loader, test environment); - Participating in development of Motor Control IC FPGA prototype (based on Cortex-M3); - Test environment system; - https://github.com/vvgulyaev/aes . - https://github.com/vvgulyaev/uvm.git

Development of test devices using FPGA for testing and parameter definition of power converters sub-modules.

Development digital signal processing RTL designs. Achievements: - http://opencores.org/project,color_converter - jpeg lossless codec

Development and verification digital circuits using Cadence Schematic.

Physics and microelectronics Department, Microelectronics and semiconductors devices physics

Coursera, Machine Learning

Cadence Trainings, Innovus implementation block & hierarchical / CCOPT

Skill Branch, Программирование на JavaScript